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CS51411, CS51412, CS51413, CS51414 1.5 A, 260 kHz and 520 kHz, Low Voltage Buck Regulators with External Bias or Synchronization Capability
The CS5141X products are 1.5 A buck regulator ICs. These devices are fixed-frequency operating at 260 kHz and 520 kHz. The regulators use the V2TM control architecture to provide unmatched transient response, the best overall regulation and the simplest loop compensation for today's high-speed logic. These products accommodate input voltages from 4.5 V to 40 V. The CS51411 and CS51413 contain synchronization circuitry. The CS51412 and CS51414 have the option of powering the controller from an external 3.3 V to 6.0 V supply in order to improve efficiency, especially in high input voltage, light load conditions. The on-chip NPN transistor is capable of providing a minimum of 1.5 A of output current, and is biased by an external "boost" capacitor to ensure saturation, thus minimizing on-chip power dissipation. Protection circuitry includes thermal shutdown, cycle-by-cycle current limiting and frequency foldback. The CS51411 and CS51413 are functionally pin-compatible with the LT1375. The CS51412 and CS51414 are functionally pin-compatible with the LT1376.
Features
8 1 SOIC-8 D SUFFIX CASE 751
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8 5141x ALYWy G 1
18
1 CS5141xy AWLYYWW G G
18
1 18-LEAD DFN MN SUFFIX CASE 505
* V2 Architecture Provides Ultrafast Transient Response, Improved * * * * * * * * * *
Regulation and Simplified Design 2.0% Error Amp Reference Voltage Tolerance Switch Frequency Decrease of 4:1 in Short Circuit Conditions Reduces Short Circuit Power Dissipation BOOST Lead Allows "Bootstrapped" Operation to Maximize Efficiency Sync Function for Parallel Supply Operation or Noise Minimization Shutdown Lead Provides Power-Down Option 85 mA Quiescent Current During Power-Down Thermal Shutdown Soft-Start Pin-Compatible with LT1375 and LT1376 Pb-Free Packages are Available
5141x = Device Code x = 1, 2, 3 or 4 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week y = E or G G = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
1
September, 2007 - Rev. 18
Publication Order Number: CS51411/D
CS51411, CS51412, CS51413, CS51414
PIN CONNECTIONS
CS51411/3
BOOST VIN VSW SHDNB 1 8 VC VFB GND SYNC BOOST VIN VIN VIN Vsw VSW VSW SHDNB NC 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 NC VC VFB NC NC GND NC NC SYNC BOOST VIN VIN VIN Vsw VSW VSW BIAS NC 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 NC VC VFB NC NC GND NC NC SHDNB
CS51411/3
CS51412/4
CS51412/4
BOOST VIN VSW BIAS 1 8 VC VFB GND SHDNB
PACKAGE PIN DESCRIPTION
SOIC-8 Package Pin # 1 DFN18 Package Pin # 1 Pin Symbol BOOST Function The BOOST pin provides additional drive voltage to the on-chip NPN power transistor. The resulting decrease in switch on voltage increases efficiency. This pin is the main power input to the IC. This is the connection to the emitter of the on-chip NPN power transistor and serves as the switch output to the inductor. This pin may be subjected to negative voltages during switch off-time. A catch diode is required to clamp the pin voltage in normal operation. This node can stand -1.0 V for less than 50 ns during switch node flyback. The BIAS pin connects to the on-chip power rail and allows the IC to run most of its internal circuitry from the regulated output or another low voltage supply to improve efficiency. The BIAS pin is left floating if this feature is not used. This pin provides the synchronization input. 10 10 (CS51412/CS51414) 8 (CS51411/CS51413) 13 16 SYNC SHDNB The shutdown pin is active low and TTL compatible. The IC goes into sleep mode, drawing less than 85 mA when the pin voltage is pulled below 1.0 V. This pin should be left floating in normal position. Power return connection for the IC. The FB pin provides input to the inverting input of the error amplifier. If VFB is lower than 0.29 V, the oscillator frequency is divided by four, and current limit folds back to about 1 A. These features protect the IC under severe overcurrent or short circuit conditions. The VC pin provides a connection point to the output of the error amplifier and input to the PWM comparator. Driving of this pin should be avoided because on-chip test circuitry becomes active whenever current exceeding 0.5 mA is forced into the IC. No Connection
2 3
2, 3, 4 5, 6, 7
VIN VSW
4 (CS51412/CS51414)
8
BIAS
5 (CS51411/CS51413) 5 (CS51412/CS51414) 4 (CS51411/CS51413) 6 7
GND VFB
8
17
VC
-
9, 11, 12, 14, 15, 18
NC
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18-Lead DFN
18-Lead DFN
CS51411, CS51412, CS51413, CS51414
PRODUCT SELECTION GUIDE
Part Number CS51411E CS51411G CS51412E CS51412G CS51413E CS51413G CS51414E CS51414G Frequency 260 kHz 260 kHz 260 kHz 260 kHz 520 kHz 520 kHz 520 kHz 520 kHz Temperature Range -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C Bias/Sync Sync Sync Bias Bias Sync Sync Bias Bias
D1 C1 0.1 mF VSW 3
1N4148
4.5 V - 16 V C2 100 mF Shutdown SYNC 4 5 SYNC VC 8 C4 0.1 mF U1 2 VIN SHDNB 1 BOOST CS51411/3 GND 6 VFB 7
3.3 V L1 15 mH D3 1N5821 R1 205
C3 100 mF
R2 127
Figure 1. Application Diagram, 4.5 V - 16 V to 3.3 V @ 1.0 A Converter
MAXIMUM RATINGS
Rating Operating Junction Temperature Range, TJ Lead Temperature Soldering: Reflow for Leaded: (SMD styles only) (Note 1) Reflow for Pb-Free: (SMD styles only) (Note 2) Value -40 to 150 230 peak 260 peak (Note 3) -65 to +150 2.0 Unit C C C kV
Storage Temperature Range, TS ESD Damage Threshold (Human Body Model)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 60-150 second above 183C, 30 second maximum at peak. 2. 60-150 second above 217C, 40 second maximum at peak. 3. +5C/0C allowable conditions, applies to both Pb and Pb-Free Devices.
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CS51411, CS51412, CS51413, CS51414
MAXIMUM RATINGS
Pin Name VIN BOOST VSW VC SHDNB SYNC BIAS VFB GND VMax 40 V 40 V 40 V 7.0 V 7.0 V 7.0 V 7.0 V 7.0 V 7.0 V VMIN -0.3 V -0.3 V -0.6 V/-1.0 V, t < 50 ns -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V ISOURCE N/A N/A 4.0 A 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 50 mA ISINK 4.0 A 100 mA 10 mA 1.0 mA 1.0 mA 1.0 mA 50 mA 1.0 mA 1.0 mA
ELECTRICAL CHARACTERISTICS (-40C < TJ < 125C (CS51411E/2E/3E/4E); -40C < TA < 85C (CS51411E/2E/3E/4E);
0C < TA < 70C (CS51411G/2G/3G/4G), 4.5 V< VIN < 40 V; unless otherwise specified.) Characteristic Oscillator Operating Frequency Operating Frequency Frequency Line Regulation Maximum Duty Cycle VFB Frequency Foldback Threshold PWM Comparator Slope Compensation Voltage Minimum Output Pulse Width Power Switch Current Limit Foldback Current Saturation Voltage Current Limit Delay Error Amplifier Internal Reference Voltage Reference PSRR FB Input Bias Current Output Source Current Output Sink Current Output High Voltage Output Low Voltage Unity Gain Bandwidth Open Loop Amplifier Gain Amplifier Transconductance (Note 4) VC = 1.270 V, VFB = 1.0 V VC = 1.270 V, VFB = 2.0 V VFB = 1.0 V VFB = 2.0 V (Note 4) (Note 4) (Note 4) 1.244 15 15 1.39 5.0 1.270 40 0.02 25 25 1.46 20 500 70 6.4 1.296 0.1 35 35 1.53 60 V dB mA mA mA V mV kHz dB mA/V VFB > 0.36 V VFB < 0.29 V IOUT = 1.5 A, VBOOST = VIN + 2.5 V (Note 4) 1.6 0.9 0.4 2.3 1.5 0.7 120 3.0 2.1 1.0 160 A A V ns CS51411/CS51412, Fix VFB, DVC/DTON CS51413/CS51414 CS51411/CS51412, VFB to VSW CS51413/CS51414, VFB to VSW 8.0 25 17 50 150 26 75 300 230 mV/ms mV/ms ns ns CS51411/CS51412 CS51413/CS51414 224 446 85 0.29 260 520 0.05 90 0.32 296 594 0.15 95 0.36 kHz kHz %/V % V Test Conditions Min Typ Max Unit
4. Guaranteed by design, not 100% tested in production.
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CS51411, CS51412, CS51413, CS51414
ELECTRICAL CHARACTERISTICS (-40C < TJ < 125C (CS51411E/2E/3E/4E); -40C < TA < 85C (CS51411E/2E/3E/4E);
0C < TA < 70C (CS51411G/2G/3G/4G), 4.5 V< VIN < 40 V; unless otherwise specified.) Characteristic Sync Sync Frequency Range Sync Frequency Range Sync Pin Bias Current Sync Threshold Voltage Shutdown Shutdown Threshold Voltage Shutdown Pin Bias Current Thermal Shutdown Overtemperature Trip Point Thermal Shutdown Hysteresis General Quiescent Current Shutdown Quiescent Current Boost Operating Current Minimum Boost Voltage Startup Voltage Minimum Output Current 5. Guaranteed by design, not 100% tested in production. ISW = 0 A VSHDNB = 0 V VBOOST - VSW = 2.5 V (Note 5) 3.0 8.0 6.0 2.2 4.0 20 15 3.3 7.0 6.25 85 40 2.5 4.4 12 mA mA mA/A V V mA (Note 5) (Note 5) 175 185 42 195 C C VSHDNB = 0 V 1.0 0.14 1.3 5.00 1.6 35 V mA CS51411/CS51412 CS51413/CS51414 VSYNC = 0 V VSYNC = 5.0 V 305 575 250 1.0 0.1 360 1.5 470 880 0.2 460 1.9 kHz kHz mA mA V Test Conditions Min Typ Max Unit
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CS51411, CS51412, CS51413, CS51414
SHDNB SYNC
VIN 5.0 mA 2.9 V LDO Voltage Regulator Shutdown Comparator + + 1.3 V S R Q
BIAS
Artificial Ramp
Oscillator
Thermal Shutdown
BOOST
Output Driver
VSW
+ PWM Com parator Current Limit Com parator IREF + VFB + 1.270 V + Error Amplifier + 0.32 V + Frequency and Current Limit Foldback IFOLDBACK GND VC
1.46 V
Figure 2. Block Diagram
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CS51411, CS51412, CS51413, CS51414
APPLICATIONS INFORMATION THEORY OF OPERATION
V2 Control
The CS5141X family of buck regulators utilizes a V2 control technique and provides a high level of integration to enable high power density design optimization. Every pulse width modulated controller configures basic control elements such that when connected to the feedback signal of a power converter, sufficient loop gain and bandwidth is available to regulate the voltage set point against line and load variations. The arrangement of these elements differentiates a voltage mode, or a current mode controller from a V2 device. Figure 3 illustrates the basic architecture of a V2 controller.
Error Amplifier + Z2 VREF VFB Clock V2 Control Ramp Z1 VO
cycle modulation to occur. Actual oscilloscope waveforms taken from the converter show the switch node VSWITCH, the error signal VC and the feedback signal VFB (AC component only) are shown in Figure 5.
S1 L1 VO R1 Duty Cycle D1 C1
VIN
Buck Controller
Slope Comp
Oscillator
Latch S R SFB
+ -
PWM Com parator V2
Control
Figure 3. V2 Control
Figure 4. Buck Converter with V2 Control
In common with V mode or I mode, the feedback signal is compared with a reference voltage to develop an error signal which is fed to one input of the PWM. The second input to the PWM, however, is neither a fixed voltage ramp nor the switch current, but rather the feedback signal from the output of the converter. This feedback signal provides both DC information as well as AC information (the control ramp) for the converter to regulate its set point. The control architecture is known as V2 since both PWM inputs are derived from the converter's output voltage. This is a little misleading because the control ramp is typically generated from current information present in the converter. The feedback signal from the buck converter shown in Figure 4 is processed in one of two ways before being routed to the inputs of the PWM comparator. The Fast Feedback path (FFB) adds slope compensation to the feedback signal before passing it to one input of the PWM. The Slow Feedback path (SFB) compares the original feedback signal against a DC reference. The error signal generated at the output of the error amplifier VC is filtered by a low frequency pole before being routed to the second input of the PWM. Each switch cycle is initiated (S1 on), when the output latch is set by the oscillator. Each switch cycle terminates (S1 off), when the FFB signal (AC plus output DC) exceeds SFB (error DC), and the output latch is reset. In the event of a load transient, the FFB signal changes faster, in relation to the filtered SFB signal, causing duty
In the event of a load transient, the FFB signal changes faster, in relation to the filtered SFB signal, causing duty cycle modulation to occur. By this means the converter's transient response time is independent of the error amplifier bandwidth. The error amplifier is used here to ensure excellent DC accuracy. In order for the controller to operate optimally, a stable ramp is required at the feedback pin.
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- +
Switch
Latch/Drive
PWM
Figure 5.
+
FFB
R2
VC
VREF
+ -
Error Amplifier
VSWITCH
VC VFB
CS51411, CS51412, CS51413, CS51414
Control Ramp Generation
In original V2 designs, the control ramp VCR was generated from the converter's output ripple. Using a current derived ramp provides the same benefits as current mode, namely input feed forward, single pole output filter compensation and fast feedback following output load transients. Typically a tantalum or organic polymer capacitor is selected having a sufficiently large ESR component, relative to its capacitive and ESL ripple contributions, to ensure the control ramp was sensing inductor current and its amplitude was sufficient to maintain loop stability. This technique is illustrated in Figure 6.
VIN L Cesr C VOUT
VIN R C
VOUT
VFB
Figure 7. Control Ramp Generated from DCR Inductor Sensing
VFB
Figure 6. Control Ramp Generated from Output
Advances in multilayer ceramic capacitor technology are such that MLCC's can provide a cost effective filter solution for low voltage (< 12 V), high frequency converters (>200 kHz). For example, a 10 mF MLCC 16 V in a 805 SMT package has an ESR of 2 mW and an ESL of 100 nH. Using several MLCC's in parallel, connected to power and ground planes on a PCB with multiple vias, can provide a "near perfect" capacitor. Using this technique, output switching ripple below 10 mV can be readily obtained since parasitic ESR and ESL ripple contributions are nil. In this case, the control ramp is generated elsewhere in the circuit. Ramp generation using dcr inductor current sensing, where the L/DCR time constant of the output inductor is matched with the CR time constant of the integrating network, is shown in Figure 7. The converter's transient response following a 1 A step load is shown in Figure 8. This transient response is indicative of a closed loop in excess of 10 kHz having good gain and phase margin in the frequency domain. Also note the amplitude of output switching ripple provided by just two 10 mF MLCC's.
Figure 8.
Ramp generation using a voltage feed forward technique is illustrated in Figure 9.
VIN Rf CZ VOUT
Cf
VFB
Figure 9. Control Ramp from Voltage Feed Forward
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CS51411, CS51412, CS51413, CS51414
Some representative efficiency data is shown in Figure 10.
100
80 EFFICIENCY (%)
60
40
Vin = 5.5 V, Vout= 3.3 V
20
Vin = 7.5 V, Vout = 5.0 V Vin = 15V, Vout = 12 V
0
0
500 1000 IOUT, OUTPUT CURRENT (mA)
1500
Figure 11. A CS51411 Buck Regulator is Synced by an External 350 kHz Pulse Signal Power Switch and Current Limit
Figure 10. Efficiency versus Output Current
More detailed information is available in the ON Semiconductor application note AND8276/D on V2 and the CS5141x demonstration board number.
Error Amplifier
VIN - VSW (V)
The CS5141X has a transconductance error amplifier, whose noninverting input is connected to an Internal Reference Voltage generated from the on-chip regulator. The inverting input connects to the VFB pin. The output of the error amplifier is made available at the VC pin. A typical frequency compensation requires only a 0.1 mF capacitor connected between the VC pin and ground, as shown in Figure 1. This capacitor and error amplifier's output resistance (approximately 8.0 MW) create a low frequency pole to limit the bandwidth. Since V2 control does not require a high bandwidth error amplifier, the frequency compensation is greatly simplified. The VC pin is clamped below Output High Voltage. This allows the regulator to recover quickly from overcurrent or short circuit conditions.
Oscillator and Sync Feature (CS51411 and CS51413 only)
The collector of the built-in NPN power switch is connected to the VIN pin, and the emitter to the VSW pin. When the switch turns on, the VSW voltage is equal to the VIN minus switch Saturation Voltage. In the buck regulator, the VSW voltage swings to one diode drop below ground when the power switch turns off, and the inductor current is commutated to the catch diode. Due to the presence of high pulsed current, the traces connecting the VSW pin, inductor and diode should be kept as short as possible to minimize the noise and radiation. For the same reason, the input capacitor should be placed close to the VIN pin and the anode of the diode. The saturation voltage of the power switch is dependent on the switching current, as shown in Figure 12.
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 SWITCHING CURRENT (A) 1.5
The on-chip oscillator is trimmed at the factory and requires no external components for frequency control. The high switching frequency allows smaller external components to be used, resulting in a board area and cost savings. The tight frequency tolerance simplifies magnetic components election. The switching frequency is reduced to 25% of the nominal value when the VFB pin voltage is below Frequency Foldback Threshold. In short circuit or overload conditions, this reduces the power dissipation of the IC and external components. An external clock signal can sync CS51411/CS51414 to a higher frequency. The rising edge of the sync pulse turns on the power switch to start a new switching cycle, as shown in Figure 11. There is approximately 0.5 ms delay between the rising edge of the sync pulse and rising edge of the VSW pin voltage. The sync threshold is TTL logic compatible, and duty cycle of the sync pulses can vary from 10% to 90%. The frequency foldback feature is disabled during the sync mode.
Figure 12. The Saturation Voltage of the Power Switch Increases with the Conducting Current
Members of the CS5141X family contain pulse-by-pulse current limiting to protect the power switch and external components. When the peak of the switching current reaches the Current Limit, the power switch turns off after the Current Limit Delay. The switch will not turn on until the next switching cycle. The current limit threshold is
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CS51411, CS51412, CS51413, CS51414
independent of switching duty cycle. The maximum load current, given by the following formula under continuous conduction mode, is less than the Current Limit due to the ripple current.
V (V * VO) IO(MAX) + ILIM * O IN 2(L)(VIN)(fs)
As shown in Figure 14, the BOOST pin current includes a constant 7.0 mA predriver current and base current proportional to switch conducting current. A detailed discussion of this current is conducted in Thermal Consideration section. A 0.1 mF capacitor is usually adequate for maintaining the Boost pin voltage during the on time.
BIAS Pin (CS51412 and CS51414 Only)
BOOST PIN CURRENT (mA)
where: fS = switching frequency, ILIM = current limit threshold, VO = output voltage, VIN = input voltage, L = inductor value. When the regulator runs undercurrent limit, the subharmonic oscillation may cause low frequency oscillation, as shown in Figure 13. Similar to current mode control, this oscillation occurs at the duty cycle greater than 50% and can be alleviated by using a larger inductor value. The current limit threshold is reduced to Foldback Current when the FB pin falls below Foldback Threshold. This feature protects the IC and external components under the power up or overload conditions.
The BIAS pin allows a secondary power supply to bias the control circuitry of the IC. The BIAS pin voltage should be between 3.3 V and 6.0 V. If the BIAS pin voltage falls below that range, use a diode to prevent current drain from the BIAS pin. Powering the IC with a voltage lower than the regulator's input voltage reduces the IC power dissipation and improves energy transfer efficiency.
30 25 20 15 10 5 0
0
0.5 1.0 SWITCHING CURRENT (A)
1.5
Figure 14. The Boost Pin Current Includes 7.0 mA Predriver Current and Base Current when the Switch is Turned On. The Beta Decline of the Power Switch Further Increases the Base Current at High Switching Current Shutdown Figure 13. The Regulator in Current Limit BOOST Pin
The BOOST pin provides base driving current for the power switch. A voltage higher than VIN provides required headroom to turn on the power switch. This in turn reduces IC power dissipation and improves overall system efficiency. The BOOST pin can be connected to an external boost-strapping circuit which typically uses a 0.1 mF capacitor and a 1N914 or 1N4148 diode, as shown in Figure 1. When the power switch is turned on, the voltage on the BOOST pin is equal to
VBOOST + VIN ) VO * VF
The internal power switch will not turn on until the VIN pin rises above the Startup Voltage. This ensures no switching until adequate supply voltage is provided to the IC. The IC enters a sleep mode when the SHDNB pin is pulled below Shutdown Threshold Voltage. In the sleep mode, the power switch keeps open and the supply current reduces to Shutdown Quiescent Current. This pin has internal pull-up current. So when this pin is not used, leave the SHDNB pin open.
Startup
where: VF = diode forward voltage. The anode of the diode can be connected to any DC voltage other than the regulated output voltage. However, the maximum voltage on the BOOST pin shall not exceed 40 V.
During power up, the regulator tends to quickly charge up the output capacitors to reach voltage regulation. This gives rise to an excessive in-rush current which can be detrimental to the inductor, IC and catch diode. In V2 control, the compensation capacitor provides Soft-Start with no need for extra pin or circuitry. During the power up, the Output Source Current of the error amplifier charges the compensation capacitor which forces VC pin and thus output voltage ramp up gradually.
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CS51411, CS51412, CS51413, CS51414
The Soft-Start duration can be calculated by
V CCOMP TSS + C ISOURCE
diode current. The short circuit waveforms are captured in Figure 16, and the benefit of the foldback frequency and current limit is self-evident.
where: VC = VC pin steady-state voltage, which is approximately equal to error amplifier's reference voltage. CCOMP = Compensation capacitor connected to the VC pin ISOURCE = Output Source Current of the error amplifier. Using a 0.1 mF CCOMP, the calculation shows a TSS over 5.0 ms which is adequate to avoid any current stresses. Figure 15 shows the gradual rise of the VC, VO and envelope of the VSW during power up. There is no voltage overshoot after the output voltage reaches the regulation. If the supply voltage rises slower than the VC pin, output voltage may overshoot.
Figure 16. In Short Circuit, the Foldback Current and Foldback Frequency Limit the Switching Current to Protect the IC, Inductor and Catch Diode Thermal Considerations
A calculation of the power dissipation of the IC is always necessary prior to the adoption of the regulator. The current drawn by the IC includes quiescent current, predriver current, and power switch base current. The quiescent current drives the low power circuits in the IC, which include comparators, error amplifier and other logic blocks. Therefore, this current is independent of the switching current and generates power equal to
Figure 15. The Power Up Transition of CS5141X Regulator Short Circuit WQ + VIN IQ
where: IQ = quiescent current. The predriver current is used to turn on/off the power switch and is approximately equal to 12 mA in worst case. During steady state operation, the IC draws this current from the Boost pin when the power switch is on and then receives it from the VIN pin when the switch is off. The predriver current always returns to the VSW pin. Since the predriver current goes out to the regulator's output even when the power switch is turned off, a minimum load is required to prevent overvoltage in light load conditions. If the Boost pin voltage is equal to VIN + VO when the switch is on, the power dissipation due to predriver current can be calculated by
WDRV + 12 mA V2 (VIN * VO ) O ) VIN
When the VFB pin voltage drops below Foldback Threshold, the regulator reduces the peak current limit by 40% and switching frequency to 1/4 of the nominal frequency. These features are designed to protect the IC and external components during overload or short circuit conditions. In those conditions, peak switching current is clamped to the current limit threshold. The reduced switching frequency significantly increases the ripple current, and thus lowers the DC current. The short circuit can cause the minimum duty cycle to be limited by Minimum Output Pulse Width. The foldback frequency reduces the minimum duty cycle by extending the switching cycle. This protects the IC from overheating, and also limits the power that can be transferred to the output. The current limit foldback effectively reduces the current stress on the inductor and diode. When the output is shorted, the DC current of the inductor and diode can approach the current limit threshold. Therefore, reducing the current limit by 40% can result in an equal percentage drop of the inductor and
The base current of a bipolar transistor is equal to collector current divided by beta of the device. Beta of 60 is used here to estimate the base current. The Boost pin provides the base current when the transistor needs to be on.
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CS51411, CS51412, CS51413, CS51414
The power dissipated by the IC due to this current is
V2 WBASE + O VIN IS 60
where: IS = DC switching current. When the power switch turns on, the saturation voltage and conduction current contribute to the power loss of a non-ideal switch. The power loss can be quantified as
WSAT + VO VIN IS VSAT
where: VSAT = saturation voltage of the power switch which is shown in Figure 12. The switching loss occurs when the switch experiences both high current and voltage during each switch transition. This regulator has a 30 ns turn-off time and associated power loss is equal to
I WS + S VIN 2 30 ns fS
Internal bias to the IC can be supplied via the Vin pin or the BIAS pin. When the BIAS pin is low, the logic turns P2 on and current is routed to the internal bias circuitry from the Vin pin. Conversely, when the BIAS pin is high, the logic turns P1 on and current is routed to the internal bias circuitry from the BIAS pin. Here is an example of the power savings: The input voltage range for Vin is 4.5 V to 40 V. The input voltage range for BIAS is 3.3 V to 6 V. The quiescent current specification is 3 mA (min), 4 mA (typ), and 6.25 mA (max). Using a typical battery voltage of 14 V and the typical quiescent current number of 4 mA, the power would be:
P+V I + 14 4e-3 + 56 mW
We'll assume the BIAS pin is connected to an external regulator at 5 V instead of the output voltage. The BIAS pin would normally be connected to the output voltage, but adding an added switching regulator efficiency number here would cloud this example. Now the internal BIAS circuitry is being powered via 5 V. The resulting on chip power being dissipated is:
P+V I+5 4e-3 + 21 mW
The turn-on time is much shorter and thus turn-on loss is not considered here. The total power dissipated by the IC is sum of all the above
WIC + WQ ) WDRV ) WBASE ) WSAT ) WS
The IC junction temperature can be calculated from the ambient temperature, IC power dissipation and thermal resistance of the package. The equation is shown as follows,
TJ + WIC RqJA ) TA
The power savings is 35 mW. Now, to demonstrate more notable savings using the maximum battery input voltage of 40 V, the maximum quiescent current of 6.25 mA, and the lowest allowed BIAS voltage for proper operation of 3.3 V; Powered from Vin:
P + 40 P + 3.3 6.25e-3 + 250 mW 6.25e-3 + 21 mW
The maximum IC junction temperature shall not exceed 125C to guarantee proper operation and avoid any damages to the IC.
Using the BIAS Pin
Powered from the BIAS pin: The power savings is 229 mW.
Minimum Load Requirement
The efficiency savings in using the BIAS pin is most notable at low load and high input voltage as will be explained below. Figure 17 will help to understand the increase in efficiency when the BIAS pin is used. The circuitry shown is not the actual implementation, but is useful in the explanation.
Internal BIAS
As pointed out in the previous section, a minimum load is required for this regulator due to the predriver current feeding the output. Placing a resistor equal to VO divided by 12 mA should prevent any voltage overshoot at light load conditions. Alternatively, the feedback resistors can be valued properly to consume 12 mA current. COMPONENT SELECTION
BIAS
P1
Input Capacitor
Vin
P2
In a buck converter, the input capacitor witnesses pulsed current with an amplitude equal to the load current. This pulsed current and the ESR of the input capacitors determine the VIN ripple voltage, which is shown in Figure 18. For VIN ripple, low ESR is a critical requirement for the input capacitor selection. The pulsed input current possesses a significant AC component, which is absorbed by the input capacitors.
Figure 17.
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CS51411, CS51412, CS51413, CS51414
The RMS current of the input capacitor can be calculated using:
IRMS + IO D(1 * D)
where: D = switching duty cycle which is equal to VO/VIN. IO = load current.
Selecting the capacitor type is determined by each design's constraint and emphasis. The aluminum electrolytic capacitors are widely available at lowest cost. Their ESR and Equivalent Series Inductor (ESL) are relatively high. Multiple capacitors are usually paralleled to achieve lower ESR. In addition, electrolytic capacitors usually need to be paralleled with a ceramic capacitor for filtering high frequency noises. The OS-CON are solid aluminum electrolytic capacitors, and therefore has a much lower ESR. Recently, the price of the OS-CON capacitors has dropped significantly so that it is now feasible to use them for some low cost designs. Electrolytic capacitors are physically large, and not used in applications where the size, and especially height is the major concern. Ceramic capacitors are now available in values over 10 mF. Since the ceramic capacitor has low ESR and ESL, a single ceramic capacitor can be adequate for both low frequency and high frequency noises. The disadvantage of ceramic capacitors are their high cost. Solid tantalum capacitors can have low ESR and small size. However, the reliability of the tantalum capacitor is always a concern in the application where the capacitor may experience surge current.
Output Capacitor
Figure 18. Input Voltage Ripple in a Buck Converter
To calculate the RMS current, multiply the load current with the constant given by Figure 19 at each duty cycle. It is a common practice to select the input capacitor with an RMS current rating more than half the maximum load current. If multiple capacitors are paralleled, the RMS current for each capacitor should be the total current divided by the number of capacitors.
0.6 0.5 0.4 IRMS (XIO) 0.3 0.2 0.1 0
In a buck converter, the requirements on the output capacitor are not as critical as those on the input capacitor. The current to the output capacitor comes from the inductor and thus is triangular. In most applications, this makes the RMS ripple current not an issue in selecting output capacitors. The output ripple voltage is the sum of a triangular wave caused by ripple current flowing through ESR, and a square wave due to ESL. Capacitive reactance is assumed to be small compared to ESR and ESL. The peak-to-peak ripple current of the inductor is:
V (V * VO) IP * P + O IN (VIN)(L)(fS)
VRIPPLE(ESR), the output ripple due to the ESR, is equal to the product of IP-P and ESR. The voltage developed across the ESL is proportional to the di/dt of the output capacitor. It is realized that the di/dt of the output capacitor is the same as the di/dt of the inductor current. Therefore, when the switch turns on, the di/dt is equal to (VIN - VO)/L, and it becomes VO/L when the switch turns off. The total ripple voltage induced by ESL can then be derived from
0 0.2 0.4 0.6 DUTY CYCLE 0.8 1.0 V * VO V V VRIPPLE(ESL) + ESL( IN) ) ESL( IN ) + ESL( IN) L L L
Figure 19. Input Capacitor RMS Current can be Calculated by Multiplying Y Value with Maximum Load Current at any Duty Cycle
The total output ripple is the sum of the VRIPPLE(ESR) and VRIPPLE(ESR).
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CS51411, CS51412, CS51413, CS51414
Figure 20. The Output Voltage Ripple Using Two 10 mF Ceramic Capacitors in Parallel
Figure 22. The Output Voltage Ripple Using One 100 mF OS-CON
Figure 21. The Output Voltage Ripple Using One 100 mF POSCAP Capacitor
Figure 23. The Output Voltage Ripple Using One 100 mF Tantalum Capacitor
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CS51411, CS51412, CS51413, CS51414
Figure 20 to Figure 23 show the output ripple of a 5.0 V to 3.3 V/500 mA regulator using 22 mH inductor and various capacitor types. At the switching frequency, the low ESR and ESL make the ceramic capacitors behave capacitively as shown in Figure 20. Additional paralleled ceramic capacitors will further reduce the ripple voltage, but inevitably increase the cost. "POSCAP", manufactured by SANYO, is a solid electrolytic capacitor. The anode is sintered tantalum and the cathode is a highly conductive polymerized organic semiconductor. TPC series, featuring low ESR and low profile, is used in the measurement of Figure 21. It is shown that POSCAP presents a good balance of capacitance and ESR, compared with a ceramic capacitor. In this application, the low ESR generates less than 5.0 mV of ripple and the ESL is almost unnoticeable. The ESL of the through-hole OS-CON capacitor give rise to the inductive impedance. It is evident from Figure 22 which shows the step rise of the output ripple on the switch turn-on and large spike on the switch turn-off. The ESL prevents the output capacitor from quickly charging up the parasitic capacitor of the inductor when the switch node is pulled below ground through the catch diode conduction. This results in the spike associated with the falling edge of the switch node. The D package tantalum capacitor used in Figure 23 has the same footprint as the POSCAP, but doubles the height. The ESR of the tantalum capacitor is apparently higher than the POSCAP. The electrolytic and tantalum capacitors provide a low-cost solution with compromised performance. The reliability of the tantalum capacitor is not a serious concern for output filtering because the output capacitor is usually free of surge current and voltage.
Diode Selection
The worse case of the diode average current occurs during maximum load current and maximum input voltage. For the diode to survive the short circuit condition, the current rating of the diode should be equal to the Foldback Current Limit. See Table 1 for Schottky diodes from ON Semiconductor which are suggested for CS5141X regulator.
Inductor Selection
When choosing inductors, one might have to consider maximum load current, core and copper losses, component height, output ripple, EMI, saturation and cost. Lower inductor values are chosen to reduce the physical size of the inductor. Higher value cuts down the ripple current, core losses and allows more output current. For most applications, the inductor value falls in the range between 2.2 mH and 22 mH. The saturation current ratings of the inductor shall not exceed the IL(PK), calculated according to
V (V * VO) IL(PK) + IO ) O IN 2(fS)(L)(VIN)
The diode in the buck converter provides the inductor current path when the power switch turns off. The peak reverse voltage is equal to the maximum input voltage. The peak conducting current is clamped by the current limit of the IC. The average current can be calculated from:
I (V * VO) ID(AVG) + O IN VIN
The DC current through the inductor is equal to the load current. The worse case occurs during maximum load current. Check the vendor's spec to adjust the inductor value undercurrent loading. Inductors can lose over 50% of inductance when it nears saturation. The core materials have a significant effect on inductor performance. The ferrite core has benefits of small physical size, and very low power dissipation. But be careful not to operate these inductors too far beyond their maximum ratings for peak current, as this will saturate the core. Powered Iron cores are low cost and have a more gradual saturation curve. The cores with an open magnetic path, such as rod or barrel, tend to generate high magnetic field radiation. However, they are usually cheap and small. The cores providing a close magnetic loop, such as pot-core and toroid, generate low electro-magnetic interference (EMI). There are many magnetic component vendors providing standard product lines suitable for CS5141X. Table 2 lists three vendors, their products and contact information.
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CS51411, CS51412, CS51413, CS51414
Table 1.
Part Number 1N5817 1N5818 1N5819 MBR0520 MBR0530 MBR0540 MBRS120 MBRS130 MBRS140 VBREAKDOWN (V) 20 30 40 20 30 40 20 30 40 IAVERAGE (A) 1.0 1.0 1.0 0.5 0.5 0.5 1.0 1.0 1.0 V(F) (V) @ IAVERAGE 0.45 0.55 0.6 0.385 0.43 0.53 0.55 0.395 0.6 Package Axial Lead Axial Lead Axial Lead SOD-123 SOD-123 SOD-123 SMB SMB SMB
Table 2.
Vendor Coiltronics Product Family UNI-Pac1/2: SMT, barrel THIN-PAC: SMT, toroid, low profile CTX: Leaded, toroid DO1608: SMT, barrel DS/DT 1608: SMT, barrel, magnetically shielded DO3316: SMT, barrel DS/DT 3316: SMT, barrel, magnetically shielded DO3308: SMT, barrel, low profile Web Site www.coiltronics.com Telephone (516) 241-7876
Coilcraft
www.coilcraft.com
(800) 322-2645
Pulse
www.pulseeng.com
(619) 674-8100
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CS51411, CS51412, CS51413, CS51414
U1 5.0 V - 12 V input C1 22 mF 2 4 5 VIN
7 VFB
BOOST 1 VSW 3
C5 0.1 mF
R2 373 D2 1N4148
SHDNB CS51411/3 SYNC GND 6 VC
15 mH L1 D1 MBR0520 C6 22 m
R3 127
8 C2 0.1 mF
C3 0.01 mF R1 50 k C4 0.1 mF
-5.0 V output
Figure 24. Additional Application Diagram, 5.0 V - 12 V to -5.0 V/400 mA Inverting Converter
D2 1N4148
D1 12 V C1 100 mF Shutdown U1 2 VIN 5 SHDNB 4 BIAS 1 BOOST 3 C1 0.1 mF VSW
1N4148
5.0 V L1 15 mH D3 1N5821 R1 373
CS51412/4 GND 6 VFB 7
C3 100 mF
VC 8 C4 0.1 mF
R2 127
Figure 25. Additional Application Diagram, 12 V to 5.0 V/1.0 A Buck Converter using the BIAS Pin
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CS51411, CS51412, CS51413, CS51414
ORDERING INFORMATION
Device CS51411ED8 CS51411ED8G CS51411EDR8 CS51411EDR8G CS51411EMNR2G CS51412ED8 CS51412ED8G CS51412EDR8 CS51412EDR8G CS51412EMNR2G CS51413ED8 CS51413ED8G CS51413EDR8 CS51413EDR8G CS51413EMNR2G CS51414ED8 CS51414ED8G CS51414EDR8 CS51414EDR8G CS51414EMNR2G CS51411GD8 CS51411GD8G CS51411GDR8 CS51411GDR8G CS51411GMNR2G CS51412GD8 CS51412GD8G CS51412GDR8 CS51412GDR8G CS51412GMNR2G CS51413GD8 CS51413GD8G CS51413GDR8 CS51413GDR8G CS51413GMNR2G CS51414GD8 CS51414GD8G CS51414GDR8 CS51414GDR8G CS51414GMNR2G 0C < TA < 70C -40C < TA < 85C Operating Temperature Range Package SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) DFN18 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) DFN18 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) DFN18 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) DFN18 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) DFN18 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) DFN18 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) DFN18 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) DFN18 (Pb-Free) Shipping 98 Units/Rail 98 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 98 Units/Rail 98 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 98 Units/Rail 98 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 98 Units/Rail 98 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 98 Units/Rail 98 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 98 Units/Rail 98 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 98 Units/Rail 98 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 98 Units/Rail 98 Units/Rail 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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CS51411, CS51412, CS51413, CS51414
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AH
-XA
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-YG C -ZH D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004) M ZY
S
J
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
PACKAGE THERMAL DATA Parameter RqJC RqJA Typical Typical SOIC-8 45 165 Unit C/W C/W
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CS51411, CS51412, CS51413, CS51414
PACKAGE DIMENSIONS
D
A B
DFN18 6x5, 0.5P CASE 505-01 ISSUE D
PIN 1 LOCATION
E
2X
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 --0.45 0.65
0.15 C
2X
0.15 C 0.10 C
18X
TOP VIEW (A3) A
0.08 C SIDE VIEW D2
18X
A1
C
SEATING PLANE
SOLDERING FOOTPRINT
5.30
18X
L
e
1 9
1
0.75
18X
K
18 10
E2
0.50 PITCH
18X
BOTTOM VIEW
b 0.10 C A B 0.05 C
NOTE 3
4.19
18X
0.30
3.24
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE THERMAL DATA Parameter RqJA Typical DFN18 35 Unit C/W
V2 is a trademark of Switch Power, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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